Description
NVIDIA is hiring an ASIC Timing Engineer to drive physical design and timing analysis/closure for GPUs, CPUs, DPUs, and SoCs at block, cluster, and full-chip levels. The role involves frontend and backend implementation work including synthesis, equivalence checking, floorplanning, timing constraint management, timing and power convergence, and ECO implementation, in a cross-functional environment. Candidates should have a master's degree or higher in Electrical or Computer Engineering, strong STA and timing convergence experience, and familiarity with industry-standard EDA tools; experience with ASIC/CPU/GPU timing, deep sub-micron nodes, AI/LLM, and physical design optimization is preferred. The posting includes a salary range, benefits, equity, and notes applications are accepted until February 16, 2026.
